1. Field of the Invention
The invention relates to the field of semiconductor memories and in particular to precharged lines in memories such as precharged bit lines.
2. Prior Art
In memory arrays, bit lines are typically used to interconnect memory cells with sense amplifiers. To speed up sensing of data coupled over the bit lines, the bit lines are often precharged to a predetermined potential. This enables, among other things, for the sense amplifiers to be optimized for a narrow dynamic range and thereby provide greater sensitivity.
The bit lines must be charged before, for example, a read cycle can occur. To speed up operation in memories, the bit lines are kept charged during inactive memory cycles. These bit lines may remain charged for considerable lengths of time because cells are not always frequently accessed. This is true for instance, in a cache memory as well as other static memories. Thus, the "pull-up" transistors used to precharge the bit lines may remain in a conductive state for relatively long periods.
When n-type pull-up transistors are used, they may exhibit leakage while conducting (subthreshold leakage) that will raise the potential of the bit line above its ideal precharged (nominal) potential. In this case, the nominal potential on the bit line will be V.sub.cc less the voltage threshold drop of the pull-up transistor if there is no leakage. If the transistor exhibits subthreshold leakage, then the bit line may be charged to a higher level than the nominal.
The commonly used current-mirror sense amplifier is optimized to operate at a potential of V.sub.cc less the threshold drop associated with the pull-up transistor, a higher potential on the bit line will deteriorate the performance of the sense amplifier. This can result in slower sensing or even failure in a self-timed system as will be discussed in the Detailed Description of the Invention.
A memory may be tested to determine if any of its pull-up transistors exhibit subthreshold leakage. This testing, however, takes a relatively long time and consequently is undesirable.
Other approaches to dealing with subthreshold leakage are described in co-pending U.S. application Ser. No. 340,246, entitled "Bit Line Level Insensitive Sense Amplifier", filed on Nov. 16, 1994 and U.S. Ser. No. 271,865, entitled "Apparatus and Method for Adjusting and Maintaining a Bit Line Precharge Level", filed on Jul. 7, 1994; both these applications are assigned to the Assignee of the present application.